CY28339
AC Electrical Specifications (continued)
Parameter
TDC
Description
DOT_48M Duty Cycle
Condition
Measurement at 1.5V
Min.
Max.
Unit
%
45
55
TPERIOD
TR / TF
TCCJ
DOT_48M Period
Measurement at 1.5V
Measured between 0.4V and 2.4V
Measurement at 1.5V
USB_48M
20.83 20.83
ns
DOT_48M Rise and Fall Times
DOT_48M Cycle to Cycle Jitter
0.5
–
1.0
ns
350
ps
TDC
USB_48M Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and 2.4V
Measurement at 1.5V
45
55
%
ns
ns
TPERIOD
USB_48M Period
20.82 20.83
TR / TF
USB_48M Rise and Fall Times
DOT_48M Cycle to Cycle Jitter
1.0
–
2.0
TCCJ
350
ps
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
ns
TPERIOD
TR / TF
TCCJ
REF Period
Measurement at 1.5V
69.827 69.855
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Measured between 0.4V and 2.4V
Measurement at 1.5V
1.0
–
4.0
V/ns
ps
1000
ENABLE/DISABLE and SETUP
When XIN is driven from external clock source
TPZL/TPZH Output Enable Delay (All Outputs)
PZL/TPZH Output Disable Delay (All Outputs)
1.0
1.0
–
10.0
10.0
3.0
–
ns
ns
ms
ns
T
TSTABLE
TSS
Clock Stabilization from Power-up
Stopclock Set Up Time
CPU_STOP# and PIC_STOP# set up time with
respect to PCIF clock to guarantee that the
effected clock will stop or start at the next PCIF
clock’s rising edge.
10.0
TSH
Stopclock Hold Time
0
–
ns
TSU
Oscillator Start-up time
When crystal meets min. 40:ꢀdevice series resis-
tance specification
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
TPCB
ꢁꢁꢄꢈ:
Measurement Point
CPUT
2pF
ꢅꢆꢇ:
ꢁꢁꢄꢈ:
TPCB
Measurement Point
CPUC
2pF
ꢃꢁꢄꢅ:
ꢃꢁꢄꢅ:
ꢁꢁꢂ:
Figure 15. 1.0V Test Load Termination
Rev 1.0,November 25, 2006
Page 15 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
