CY28339
Charlene: Mult0 is FIXED at 1.
Table 4. CPU Clock Current Select Function
Board Target Trace/Term Z
Reference R, Iref – Vdd (3*Rr)
Rr = 330 1%, Iref = 3.33mA
Rr = 475 1%, Iref = 2.32mA
Output Current
Ioh = 6*Iref
Voh @ Z
1.0V @ 50
0.7V @ 50
50:
50:
Ioh = 6*Iref
Table 5. Group Timing Relationship and Tolerances
Description
Offset
2.5 ns
0.0 ns
2.5 ns
Tolerance
r1.0 ns
Conditions
3V66 to PCI
3V66 leads PCI (unbuffered mode)
0 degrees phase shift
USB_48M to DOT_48M Skew
66BUFF(0:2) to PCI offset
r1.0 ns
r1.0 ns
66BUFF leads PCI (buffered mode)
USB_48M and DOT_48M Phase Relationship
66BUFF(0:2) to PCI Buffered Clock Skew
The USB_48M and DOT_48M clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See Figure 11.
Figure 13 shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
66IN to 66BUFF(0:2) Buffered Prop Delay
3V66 to PCI Un-Buffered Clock Skew
The 66IN to 66BUFF(0:2) output delay is shown in
Figure 12.The Tpd is the prop delay from the input pin (66IN)
to the output pins (66BUFF[0:2]). The outputs’ variation of Tpd
is described in the AC parameters section of this data sheet.
The measurement taken at 1.5V.
Figure 1 shows the timing relationship between 3V66_0 and
PCI(0:2,4:8) and PCIF when configured to run in the unbuf-
fered mode.
USB_48M
DOT_48M
Figure 11. USB_48M and DOT_48M Phase Relationship
66IN
66B
Tpd
Figure 12. 66IN to 66BUFF(0:2) Output Delay Figure
66B
1.5-
3.5ns
PCI
PCIF
Figure 13. Buffer Mode – 33V66_0; 66BUFF(0:2) Phase Relationship
Rev 1.0,November 25, 2006
Page 11 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
