CY28316
CY28316 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Write with 1" must be written to “1”
during initialization.
Byte 0: Control Register 0
Bit
Pin#
Name
Spread Select1
SEL2
Default
Description
See definition in Bit[0].
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
–
–
–
–
–
0
0
0
0
0
See Table 5.
See Table 5.
See Table 5.
SEL1
SEL0
FS_Override
0 = Select operating frequency by FS[4:0] input pins.
1 = Select operating frequency by SEL[4:0] settings.
Bit 2
Bit 1
Bit 0
–
–
–
SEL4
0
0
0
See Table 5.
See Table 5.
‘00’ = OFF.
SEL3
Spread Select0
‘01’ = – 0.5%.
‘10’ = 0.5%.
‘11’ = 0.25%.
Byte 1: Control Register 1
Bit
Bit 7
Pin#
6
Name
Default
Description
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
CPU0
X
X
X
X
X
1
Latched FS[4:0] inputs. These bits are read-only.
Bit 6
7
Bit 5
46
25
26
44
43
–
Bit 4
Bit 3
Bit 2
(Active/Inactive).
(Active/Inactive).
Write with ‘1.’
Bit 1
CPU1
1
Bit 0
Vendor Test Mode
1
Byte 2: Control Register 2
Bit
Bit 7
Pin#
40
6
Name
SDRAM12
PCI0
Default
Description
(Active/Inactive).
1
1
1
1
1
1
1
1
Bit 6
(Active/Inactive).
Bit 5
13
12
11
10
9
PCI6
(Active/Inactive).
Bit 4
PCI5
(Active/Inactive).
Bit 3
PCI4
(Active/Inactive).
Bit 2
PCI3
(Active/Inactive).
Bit 1
PCI2
(Active/Inactive).
Bit 0
7
PCI1
(Active/Inactive).
Rev 1.0,November 20, 2006
Page 5 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
