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CY28316PVCT 参数 Datasheet PDF下载

CY28316PVCT图片预览
型号: CY28316PVCT
PDF下载: 下载PDF文件 查看货源
内容描述: FTG威盛PL133T和PLE133T [FTG for VIA PL133T and PLE133T]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 17 页 / 207 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28316  
FTG for VIA PL133T and PLE133T  
Features  
• Single-chip system frequency synthesizer for VIA  
PL133T and PLE133T chipsets  
• Vendor ID and Revision ID support  
• Programmable drive strength for SDRAM and PCI  
output clocks  
• Programmable clock output frequency with less than  
1 MHz increment  
• Programmable output skew for CPU, PCI, and SDRAM  
• Integrated fail-safe Watchdog Timer for system  
recovery  
• Maximized electromagnetic interference (EMI)  
suppression using Cypress’s Spread Spectrum  
technology  
• Automatically switches to HW-selected or  
SW-programmed clock frequency when Watchdog  
Timer time-out occurs  
• Available in 48-pin SSOP  
Key Specifications  
• Capable of generating system RESET after a Watchdog  
Timer time-out occurs or a change in output frequency  
via SMBus interface  
CPU to CPU Output Skew:......................................... 175 ps  
PCI to PCI Output Skew: ............................................ 500 ps  
• SupportsSMBusbyteRead/WriteandblockRead/Write  
operations to simplify system BIOS development  
[1]  
Block Diagram  
Pin Configuration  
VDD_REF  
REF0  
VDD_REF  
GND_REF  
X1  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VTT_PWRGD#  
REF0  
REF1/FS2*  
GND_CPU  
CPU0  
CPU1  
VDD_CPU  
RST#  
SDRAM_12  
GND_SDRAM  
SDRAM0  
SDRAM1  
VDD_SDRAM  
SDRAM2  
SDRAM3  
GND_SDRAM  
SDRAM4  
SDRAM5  
VDD_SDRAM  
SDRAM6  
1
2
3
4
5
6
7
8
REF1/FS2*  
X1  
X2  
XTAL  
OSC  
X2  
PLL Ref Freq  
VDD_PCI  
*FS4/PCI0  
*FS3/PCI1  
GND_PCI  
PCI2  
9
VTTPWRGD#  
PCI3  
PCI4  
PCI5  
PCI6  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CPU0:1  
PLL 1  
÷2,3,4  
VDD_PCI  
SDRAMIN  
GND_SDRAM  
SDRAM11  
SDRAM10  
VDD_SDRAM  
SDRAM9  
SDRAM8  
GND_SDRAM  
SDATA  
VDD_PCI  
PCI0/FS4*  
PCI1/FS3*  
PCI2:6  
SDATA  
SCLK  
SMBus  
Logic  
Reset  
Logic  
SDRAM7  
RST#  
VDD_48MHz  
48MHz/FS0*  
24_48MHz/FS1*  
VDD_48MHz  
48MHz/FS0*  
PLL2  
SMBus  
{
SCLK  
÷2  
24_48MHz/FS1*  
VDD_SDRAM  
SDRAM0:12  
SDRAMIN  
13  
Note:  
1. Signals marked with ‘*’ have internal pull-up resistors.  
Rev 1.0, November 20, 2006  
Page 1 of 17  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com