CY28301
Byte 2: Control Register 2
Bit
Bit 7
Pin#
20
19
17
16
15
13
12
11
Name
Default
Description
Description
Description
Description
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
1
1
1
1
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 3: Control Register 3
Bit
Bit 7
Pin#
Name
3V66_2
Default
8
7
1
1
1
1
0
0
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Reserved
Bit 6
3V66_1
3V66_0
APIC
Bit 5
6
Bit 4
54
–
Bit 3
Reserved
Reserved
CPU1
Bit 2
–
Reserved
Bit 1
51
52
(Active/Inactive)
(Active/Inactive)
Bit 0
CPU0
Byte 4: Control Register 4
Bit
Bit 7
Pin#
39
40
42
43
44
46
47
48
Name
Default
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
1
1
1
1
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 5: Control Register 5
Bit
Bit 7
Pin#
–
Name
Default
Reserved
Reserved
Reserved
SDRAM_F
SDRAM11
SDRAM10
SDRAM9
SDRAM8
0
0
0
1
1
1
1
1
Reserved
Bit 6
–
Reserved
Bit 5
–
Reserved
Bit 4
38
26
27
30
31
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 3
Bit 2
Bit 1
Bit 0
Byte 6: Vendor ID and Revision ID Register (Read-only)
Bit
Name
Default
Pin Description
Bit 7
Bit 6
Revision_ID3
Revision_ID2
0
0
Revision ID bit[3]
Revision ID bit[2]
Rev 1.0,November 27, 2006
Page 6 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
