CY28301
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
CY28301 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
3. All register bits labeled “Initialize to 0" must be written to “0”
during initialization.
Byte 0: Control Register 0
Bit
Pin#
Name
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
–
–
–
–
–
SEL1
SEL0
0
0
0
0
0
See 5
See 5
Reserved
Reserved
Reserved
Reserved
FS_Override
0 = Select operating frequency by FS[1:0] input pins
1 = Select operating frequency by SEL[1:0] settings
Bit 2
Bit 1
Bit 0
–
–
–
Spread Select2
Spread Select1
Spread Select0
0
0
0
‘000’ = Normal (spread off)
‘001’ = Test mode
‘010’ = Reserved
‘011’ = Three-stated
‘100’ = –0.5%
‘101’ = –0.75%
‘110’ = –1.0%
‘111’ = –0.3%
Byte 1: Control Register 1
Bit
Bit 7
Pin#
56
34
–
Name
Latched FS1 input
Latched FS0 input
Reserved
Default
Description
X
X
0
0
0
0
1
0
Latched FS[1:0] inputs. These bits are Read-only.
Bit 6
Bit 5
Reserved
Bit 4
–
Reserved
Reserved
Bit 3
–
Reserved
Reserved
Bit 2
–
Reserved
Reserved
Bit 1
56
56
REF
(Active/Inactive)
Bit 0
REF_DRV
REF Clock output drive strength
0 = Normal
1= High drive
Rev 1.0,November 27, 2006
Page 5 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
