CY2277A
Timing Requirement for the SMBus
Parameter
Description
Min.
0
Max.
Unit
kHz
Ps
t10
t11
t12
t13
t14
t15
t16
SCLK Clock Frequency
100
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated.
The LOW period of the clock.
4.7
4
Ps
4.7
4
Ps
The HIGH period of the clock.
Ps
Setup time for start condition. (Only relevant for a repeated start condition.)
4.7
Ps
Hold time DATA
for CBUS compatible masters.
for SMBus devices
Ps
5
0
t17
t18
t19
t20
DATA input set-up time
250
ns
Ps
ns
Ps
Rise time of both SDATA and SCLK inputs
Fall time of both SDATA and SCLK inputs
Set-up time for stop condition
1
300
4.0
Switching Waveforms
Duty Cycle Timing
t
1B
t
1A
CPUCLK Outputs HIGH/LOW Time
t
1C
VDD
0V
OUTPUT
t
1D
All Outputs Rise/Fall Time
VDD
0V
OUTPUT
t
2
t
3
t
2
t
4
Rev 1.0,November 25, 2006
Page 13 of 18