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CY2277APVC-12 参数 Datasheet PDF下载

CY2277APVC-12图片预览
型号: CY2277APVC-12
PDF下载: 下载PDF文件 查看货源
内容描述: Pentium㈢ / II , 6X86 , K6时钟合成器/驱动器,用于桌面/移动PC与Intel㈢ 82430TX和2个DIMM或3 SO- DIMM内存模块 [Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel㈢ 82430TX and 2 DIMMs or 3 SO-DIMMs]
分类和应用: 晶体驱动器外围集成电路光电二极管PC时钟
文件页数/大小: 18 页 / 293 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY2277A  
Timing Requirement for the SMBus  
Parameter  
Description  
Min.  
0
Max.  
Unit  
kHz  
Ps  
t10  
t11  
t12  
t13  
t14  
t15  
t16  
SCLK Clock Frequency  
100  
Time the bus must be free before a new transmission can start  
Hold time start condition. After this period the first clock pulse is generated.  
The LOW period of the clock.  
4.7  
4
Ps  
4.7  
4
Ps  
The HIGH period of the clock.  
Ps  
Setup time for start condition. (Only relevant for a repeated start condition.)  
4.7  
Ps  
Hold time DATA  
for CBUS compatible masters.  
for SMBus devices  
Ps  
5
0
t17  
t18  
t19  
t20  
DATA input set-up time  
250  
ns  
Ps  
ns  
Ps  
Rise time of both SDATA and SCLK inputs  
Fall time of both SDATA and SCLK inputs  
Set-up time for stop condition  
1
300  
4.0  
Switching Waveforms  
Duty Cycle Timing  
t
1B  
t
1A  
CPUCLK Outputs HIGH/LOW Time  
t
1C  
VDD  
0V  
OUTPUT  
t
1D  
All Outputs Rise/Fall Time  
VDD  
0V  
OUTPUT  
t
2
t
3
t
2
t
4
Rev 1.0,November 25, 2006  
Page 13 of 18  
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