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CY2277APVC-12 参数 Datasheet PDF下载

CY2277APVC-12图片预览
型号: CY2277APVC-12
PDF下载: 下载PDF文件 查看货源
内容描述: Pentium㈢ / II , 6X86 , K6时钟合成器/驱动器,用于桌面/移动PC与Intel㈢ 82430TX和2个DIMM或3 SO- DIMM内存模块 [Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel㈢ 82430TX and 2 DIMMs or 3 SO-DIMMs]
分类和应用: 晶体驱动器外围集成电路光电二极管PC时钟
文件页数/大小: 18 页 / 293 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY2277APVC-12的Datasheet PDF文件第7页浏览型号CY2277APVC-12的Datasheet PDF文件第8页浏览型号CY2277APVC-12的Datasheet PDF文件第9页浏览型号CY2277APVC-12的Datasheet PDF文件第10页浏览型号CY2277APVC-12的Datasheet PDF文件第12页浏览型号CY2277APVC-12的Datasheet PDF文件第13页浏览型号CY2277APVC-12的Datasheet PDF文件第14页浏览型号CY2277APVC-12的Datasheet PDF文件第15页  
CY2277A  
Switching Characteristics (-12)[9, 10, 11]  
Parameter  
Output  
Description  
Test Conditions  
t1 = t1A y t1B  
Between 0.6V and 1.8V, VDDCPU = 2.5V 1.0  
Min. Typ. Max.  
Unit  
%
t1  
t2  
All Clocks Output Duty Cycle[12]  
45  
50  
55  
CPUCLK, CPU and IOAPIC Clock  
4.0  
4.0  
V/ns  
IOAPIC  
PCI  
Rising and Falling Edge Between 0.4V and 2.4V, VDDCPU = 3.3V 1.0  
Rate  
CPU clocks at 66.6 MHz  
t2  
t2  
t2  
t2  
PCI Clock Rising and  
Falling Edge Rate  
Between 0.4V and 2.4V, VDDCPU = 3.3V 1.0  
4.0  
4.0  
4.0  
2.0  
V/ns  
V/ns  
V/ns  
V/ns  
REF0  
SDRAM  
REF0 Clock Rising and  
Falling Edge Rate  
Between 0.8V and 2.4V, VDDCPU = 3.3V 1.0  
SDRAM Rising and  
Falling Edge Rate  
Between 0.5V and 2.0V  
SDRAM clocks at 66.6 MHz  
1.5  
0.5  
REF1  
USBCLK  
IOCLK  
REF1,USBandIORising Between 0.4V and 2.4V  
and Falling Edge Rate  
t3  
t3  
t4  
t4  
CPUCLK  
CPU Clock Rise Time  
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.4  
Between 0.4V and 2.4V, VDDCPU = 3.3V 0.4  
2.0  
2.0  
ns  
ns  
ns  
ns  
USBCLK, USB Clock and I/O Clock Between 0.4V and 2.4V  
Rise Time  
1.0  
4.0  
IOCLK  
CPUCLK  
CPU Clock Fall Time  
Between 2.0V and 0.4V, VDDCPU = 2.5V 0.4  
Between 2.4V and 0.4V, VDDCPU = 3.3V 0.4  
2.0  
2.0  
USBCLK, USB Clock and I/O Clock Between 2.4V and 0.4V  
Fall Time  
1.0  
4.0  
IOCLK  
t5  
t6  
CPUCLK  
CPU-CPU Clock Skew  
Measured at 1.25V, VDDCPU = 2.5V  
100  
250  
4.0  
ps  
ns  
CPUCLK, CPU-PCI Clock Skew  
PCICLK (-12)  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
1.0  
t7  
t8  
CPUCLK, CPU-SDRAM Clock  
Skew  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks, VDDCPU = 2.5V  
500  
250  
ps  
ps  
SDRAM  
CPUCLK  
Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks and  
at 1.5V for 3.3V clocks  
t8  
t9  
PCICLK  
Cycle-Cycle Clock Jitter Measured at 1.5V  
500  
3
ps  
CPUCLK, Power-up Time  
PCICLK,  
SDRAM  
CPU, PCI, and SDRAM clock stabili-  
zation from power-up  
ms  
t10  
CPU, PCI, Frequency Slew Rate  
SDRAM  
Rate of change of frequency  
2
MHz/  
ms  
Rev 1.0,November 25, 2006  
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