CY2277A
Switching Characteristics (-12I)[9, 10, 11]
Parameter
Output
Description
Test Conditions
t1 = t1A y t1B
Between 0.6V and 1.8V, VDDCPU = 2.5V 1.0
Min. Typ. Max.
Unit
%
t1
t2
All Clocks Output Duty Cycle[12]
45
50
55
CPUCLK, CPU and IOAPIC Clock
4.0
4.0
V/ns
IOAPIC
PCI
Rising and Falling Edge Between 0.4V and 2.4V, VDDCPU = 3.3V
.8
Rate
CPU clocks at 66.6 MHz
t2
t2
t2
t2
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V
.9
4.0
4.0
4.0
2.0
V/ns
V/ns
V/ns
V/ns
REF0
SDRAM
REF0 Clock Rising and
Falling Edge Rate
Between 0.8V and 2.4V, VDDCPU = 3.3V 1.0
SDRAM Rising and
Falling Edge Rate
Between 0.5V and 2.0V
SDRAM clocks at 66.6 MHz
1
REF1
USBCLK
IOCLK
REF1,USBandIORising Between 0.4V and 2.4V
and Falling Edge Rate
0.5
t3
t3
t4
t4
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.4
Between 0.4V and 2.4V, VDDCPU = 3.3V 0.4
3.0
2.0
ns
ns
ns
ns
USBCLK, USB Clock and I/O Clock Between 0.4V and 2.4V
Rise Time
1.0
4.0
IOCLK
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V 0.4
Between 2.4V and 0.4V, VDDCPU = 3.3V 0.4
3.0
2.0
USBCLK, USB Clock and I/O Clock Between 2.4V and 0.4V
Fall Time
1.0
4.0
IOCLK
t5
t6
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
100
250
4.0
ps
ns
CPUCLK, CPU-PCI Clock Skew
PCICLK (-12)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.0
t7
t8
CPUCLK, CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
625
350
ps
ps
SDRAM
CPUCLK
Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks, VDDCPU =2.5V
t8
t9
PCICLK
Cycle-Cycle Clock Jitter Measured at 1.5V
500
3
ps
CPUCLK, Power-up Time
PCICLK,
SDRAM
CPU, PCI, and SDRAM clock stabili-
zation from power-up
ms
t10
CPU, PCI, Frequency Slew Rate
SDRAM
Rate of change of frequency
2
MHz/
ms
Rev 1.0,November 25, 2006
Page 12 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
