D a t a S h e e t ( P r e l i m i n a r y )
13. Advance Information on S29GL-R 65 nm MirrorBit Hardware
Reset (RESET#) and Power-up Sequence
Table 13.1 Hardware Reset (RESET#)
Parameter
Description
Limit
Min
Time
35
Unit
µs
t
RESET# Low to CE# Low
RESET# Pulse Width
RPH
t
Min
200
200
ns
RP
t
Time between RESET# (high) and CE# (low)
Min
ns
RH
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Figure 13.1 Reset Timings
tRP
RESET#
CE#
tRH
tRPH
Note
The sum of t and t must be equal to or greater than t .
RPH
RP
RH
Table 13.2 Power-Up Sequence Timings
Parameter
Description
Limit
Min
Min
Min
Min
Min
Time
300
300
35
Unit
µs
t
V
V
Setup Time to first access
Setup Time to first access
VCS
CC
t
µs
VIOS
IO
t
RESET# Low to CE# Low
µs
RPH
t
RESET# Pulse Width
200
200
ns
RP
t
Time between RESET# (high) and CE# (low)
ns
RH
Notes
1.
V
< V + 200 mV.
CC
IO
2.
V
and V ramp must be in sync during power-up. If RESET# is not stable for 500 µs, the following conditions may occur: the device
IO
CC
does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum V power up current is 20 mA (RESET# =V ).
CC
IL
Figure 13.2 Power-On Reset Timings
VCC
VIO
tVIOS
t VCS
tRP
RESET#
CE#
tRH
tRPH
Note
The sum of t and t must be equal to or greater than t .
RP
RH
RPH
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
75
SPANSION [ SPANSION ]
