A d v a n c e I n f o r m a t i o n
AC Characteristics
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
1
ms
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
1
ms
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
1
50
20
0
ms
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated,
the RESET# pin needs to be held low only for 100µs for power-up..
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 13. Reset Timings
92
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
SPANSION [ SPANSION ]
