D a t a S h e e t
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides
data protection against inadvertent writes (refer to Table 12 on page 63 and Table 14 on
page 65 for command definitions). In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and power-down transitions, or from sys-
tem noise.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data
during VCC power-up and power-down. The command register and all internal program/erase
circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins
to prevent unintentional writes when VCC is greater than VLKO
.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To ini-
tiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands
on the rising edge of WE#. The internal state machine is automatically reset to the read mode
on power-up.
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit™ Flash Family
45
SPANSION [ SPANSION ]
