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S29GL256M10TAIR10 参数 Datasheet PDF下载

S29GL256M10TAIR10图片预览
型号: S29GL256M10TAIR10
PDF下载: 下载PDF文件 查看货源
内容描述: 3.0伏只页面模式闪存具有0.23微米的MirrorBit制程技术 [3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 160 页 / 4686 K
品牌: SPANSION [ SPANSION ]
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P r e l i m i n a r y  
DQ2 toggles when the system reads at addresses within those sectors that have  
been selected for erasure. (The system may use either OE# or CE# to control the  
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or  
is erase-suspended. DQ6, by comparison, indicates whether the device is actively  
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected  
for erasure. Thus, both status bits are required for sector and mode information.  
Refer to Table 33 to compare outputs for DQ2 and DQ6.  
Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2:  
Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsec-  
tion. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the  
differences between DQ2 and DQ6 in graphical form.  
Reading Toggle Bits DQ6/DQ2  
Refer to Figure 8 for the following discussion. Whenever the system initially be-  
gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, the system would note and  
store the value of the toggle bit after the first read. After the second read, the  
system would compare the new value of the toggle bit with the first. If the toggle  
bit is not toggling, the device has completed the program or erase operation. The  
system can read array data on DQ7–DQ0 on the following read cycle.  
However, if after the initial two read cycles, the system determines that the toggle  
bit is still toggling, the system also should note whether the value of DQ5 is high  
(see the section on DQ5). If it is, the system should then determine again  
whether the toggle bit is toggling, since the toggle bit may have stopped toggling  
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-  
cessfully completed the program or erase operation. If it is still toggling, the  
device did not completed the operation successfully, and the system must write  
the reset command to return to reading array data.  
The remaining scenario is that the system initially determines that the toggle bit  
is toggling and DQ5 has not gone high. The system may continue to monitor the  
toggle bit and DQ5 through successive read cycles, determining the status as de-  
scribed in the previous paragraph. Alternatively, it may choose to perform other  
system tasks. In this case, the system must start at the beginning of the algo-  
rithm when it returns to determine the status of the operation (top of Figure 6).  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program, erase, or write-to-buffer time has ex-  
ceeded a specified internal pulse count limit. Under these conditions DQ5  
produces a “1,” indicating that the program or erase cycle was not successfully  
completed.  
The device may output a “1” on DQ5 if the system tries to program a “1” to a  
location that was previously programmed to “0.Only an erase operation can  
change a “0” back to a “1.” Under this condition, the device halts the opera-  
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”  
In all these cases, the system must write the reset command to return the device  
to the reading the array (or to erase-suspend-read if the device was previously  
in the erase-suspend-program mode).  
DQ3: Sector Erase Timer  
After writing a sector erase command sequence, the system may read DQ3 to de-  
termine whether or not erasure has begun. (The sector erase timer does not  
April 30, 2004 S29GLxxxM_00A5  
S29GLxxxM MirrorBitTM Flash Family  
119  
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