A d v a n c e I n f o r m a t i o n
AC Characteristics
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
70
90
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
70
90
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
70
90
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
70
30
25
25
90
35
30
30
ns
ns
ns
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Read
0
Output Enable
tOEH
Hold Time (Note 1)
Toggle and Data# Polling
Min
10
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
Min
0
ns
Notes:
1. Not 100% tested.
2. See Figure 12, on page 48 and Table 19 on page 48 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operations Timings
50
S29AL032D
S29AL032D_00_A3 June 13, 2005
SPANSION [ SPANSION ]
