A d v a n c e I n f o r m a t i o n
tion. Figure 22, on page 57 shows the toggle bit timing diagram. Figure 23, on page 58 shows
the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7, on page 43 for the following discussion. Whenever the system initially begins
reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after
the first read. After the second read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has completed the program or erase
operation. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation (top of Figure 7, on page
43).
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