A d v a n c e I n f o r m a t i o n
AC Characteristics
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
tACC
tCE
VA
VA
VA
CE#
tCH
tOE
OE#
tOEH
tDF
tOH
WE#
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
44
S29AL004D
S29AL004D_00_A1 February 18, 2005
SPANSION [ SPANSION ]
