MBM29F040C-55/-70/-90
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (see Write Operation Status section.) at which time the device returns to read the
mode.
Figure 14 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (Any address location within the desired sector.) is latched on the falling edge of WE, while the command
(Data = 30H) is latched on the rising edge of WE. A time-out of 50 µs from the rising edge of the last sector
erase command will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be
concurrently erased. The time between writes must be less than 50 µs, otherwise that command will not be
accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the
rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of
the WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase
timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or
Erase Suspend during this time-out period will reset the device to read mode, ignoring the previous command
string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart
the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector
Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of
sectors (1 to 7).
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.)
at which time the device returns to read mode. During the execution of the Sector Erase command, only the
Erase Suspend and Erase Resume commands are allowed. All other commands will reset the device to read
mode. Data polling must be performed at an address within any of the sectors being erased.
Figure 14 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
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