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MBM29DL163BE-70TN 参数 Datasheet PDF下载

MBM29DL163BE-70TN图片预览
型号: MBM29DL163BE-70TN
PDF下载: 下载PDF文件 查看货源
内容描述: 闪存的CMOS 16M ( 2M ×8 / 1M ×16 )位双操作 [FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 76 页 / 1048 K
品牌: SPANSION [ SPANSION ]
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MBM29DL16XTE/BE70/90  
Hardware Sequence Flags Table  
Status  
Embedded Program Algorithm  
Embedded Erase Algorithm  
DQ7  
DQ6  
DQ5 DQ3  
DQ2  
1
DQ7 Toggle  
0
0
0
1
0
1
Toggle  
1
Toggle*1  
Erase Suspend Read  
(Erase Suspended Sector)  
0
0
Toggle  
Erase  
Erase Suspend Read  
Suspended  
In Progress Mode  
Data Data Data Data Data  
1 *2  
(Non-Erase Suspended Sector)  
Erase Suspend Program  
(Non-Erase Suspended Sector)  
DQ7 Toggle  
0
0
Program Suspend Read  
(Program Suspended Sector)  
Data Data Data Data Data  
Data Data Data Data Data  
Program  
Suspended  
Mode  
Program Suspend Read  
(Non-Program Suspended Sector)  
Embedded Program Algorithm  
Embedded Erase Algorithm  
Erase  
DQ7 Toggle  
Toggle  
1
1
0
1
1
0
N/A  
Exceeded  
Time Limits  
Erase Suspend Program  
Suspended  
Mode  
DQ7 Toggle  
1
0
N/A  
(Non-Erase Suspended Sector)  
*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.  
*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit.  
• DQ7  
Data Polling  
The MBM29DL16XTE/BE devices feature Data Polling as a method to indicate to the host that the Embedded  
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the  
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program  
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded  
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the  
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart  
for Data Polling (DQ7) is shown in “(3) Data Polling Algorithm” in FLOW CHART.  
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse  
sequence.  
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six  
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased  
and not a protected sector. Otherwise, the status may not be valid.  
If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then  
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for  
erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.  
Once the Embedded Algorithm operation is close to being completed, the MBM29DL16XTE/BE data pins (DQ7)  
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are  
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