D A T A S H E E T
TEST CONDITIONS
Table 6. Test Specifications
5.0 V
Test Condition
Output Load
-45
All others Unit
1 TTL gate
100
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
5
pF
C
L
Input Rise and Fall Times
Input Pulse Levels
20
ns
V
6.2 kΩ
0.0–3.0 0.45–2.4
Input timing measurement
reference levels
1.5
1.5
0.8
2.0
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 7. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
20
Am29F010B
Am29F010B_00_C7 October 31, 2006
SPANSION [ SPANSION ]
