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AM29DL640H70WHI 参数 Datasheet PDF下载

AM29DL640H70WHI图片预览
型号: AM29DL640H70WHI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(8M ×8位/ 4米x 16位) CMOS 3.0伏只,同步读/写闪存 [64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 54 页 / 1243 K
品牌: SPANSION [ SPANSION ]
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Logical Inhibit  
Write cycles are inhibited by holding any one of OE# =  
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,  
CE# and WE# must be a logical zero while OE# is a  
logical one.  
START  
If data = 00h,  
SecSi Sector is  
unprotected.  
If data = 01h,  
SecSi Sector is  
protected.  
RESET# =  
VIH or VID  
Power-Up Write Inhibit  
If WE# = CE# = VIL and OE# = VIH during power up,  
the device does not accept commands on the rising  
edge of WE#. The internal state machine is automati-  
cally reset to the read mode on power-up.  
Wait 1 μs  
Write 60h to  
any address  
Remove VIH or VID  
from RESET#  
COMMON FLASH MEMORY INTERFACE  
(CFI)  
Write 40h to SecSi  
Sector address  
with A6 = 0,  
Write reset  
command  
The Common Flash Interface (CFI) specification out-  
lines device and host system software interrogation  
handshake, which allows specific vendor-specified  
software algorithms to be used for entire families of  
devices. Software support can then be device-inde-  
pendent, JEDEC ID-independent, and forward- and  
backward-compatible for the specified flash device  
families. Flash vendors can standardize their existing  
interfaces for long-term compatibility.  
A1 = 1, A0 = 0  
SecSi Sector  
Protect Verify  
complete  
Read from SecSi  
Sector address  
with A6 = 0,  
A1 = 1, A0 = 0  
This device enters the CFI Query mode when the sys-  
tem writes the CFI Query command, 98h, to address  
55h in word mode (or address AAh in byte mode), any  
time the device is ready to read array data. The  
system can read CFI information at the addresses  
given in Tables 8–11. To terminate reading CFI data,  
the system must write the reset command.The CFI  
Query mode is not accessible when the device is exe-  
cuting an Embedded Program or embedded Erase al-  
gorithm.  
Figure 3. Secured Silicon Sector Protect Verify  
Hardware Data Protection  
The command sequence requirement of unlock cycles  
for programming or erasing provides data protection  
against inadvertent writes (refer to Table 12 for com-  
mand definitions). In addition, the following hardware  
data protection measures prevent accidental erasure  
or programming, which might otherwise be caused by  
spurious system level signals during VCC power-up  
and power-down transitions, or from system noise.  
The system can also write the CFI query command  
when the device is in the autoselect mode. The device  
enters the CFI query mode, and the system can read  
CFI data at the addresses given in Tables 8–11. The  
system must write the reset command to reading array  
data.  
Low VCC Write Inhibit  
When VCC is less than VLKO, the device does not ac-  
cept any write cycles. This protects data during VCC  
power-up and power-down. The command register  
and all internal program/erase circuits are disabled,  
and the device resets to the read mode. Subsequent  
writes are ignored until VCC is greater than VLKO. The  
system must provide the proper signals to the control  
pins to prevent unintentional writes when VCC is  
For further information, please refer to the CFI Specifi-  
cation and CFI Publication 100, available via the World  
Wide Web at http://www.amd.com/flash/cfi. Alterna-  
tively, contact an AMD representative for copies of  
these documents.  
greater than VLKO  
.
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE#, CE#  
or WE# do not initiate a write cycle.  
June 7, 2005  
Am29DL640H  
19  
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