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AM29DL640H70WHI 参数 Datasheet PDF下载

AM29DL640H70WHI图片预览
型号: AM29DL640H70WHI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(8M ×8位/ 4米x 16位) CMOS 3.0伏只,同步读/写闪存 [64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 54 页 / 1243 K
品牌: SPANSION [ SPANSION ]
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draws CMOS standby current (ICC4). If RESET# is held  
at VIL but not within VSS±0.3 V, the standby current will  
be greater.  
Automatic Sleep Mode  
The automatic sleep mode minimizes Flash device en-  
ergy consumption. The device automatically enables  
this mode when addresses remain stable for tACC  
+
The RESET# pin may be tied to the system reset cir-  
cuitry. A system reset would thus also reset the Flash  
memory, enabling the system to read the boot-up firm-  
ware from the Flash memory.  
30 ns. The automatic sleep mode is independent of  
the CE#, WE#, and OE# control signals. Standard ad-  
dress access timings provide new data when ad-  
dresses are changed. While in sleep mode, output  
data is latched and always available to the system.  
ICC5 in the DC Characteristics table represents the  
automatic sleep mode current specification.  
If RESET# is asserted during a program or erase op-  
eration, the RY/BY# pin remains a “0” (busy) until the  
internal reset operation is complete, which requires a  
time of tREADY (during Embedded Algorithms). The sys-  
tem can thus monitor RY/BY# to determine whether  
the reset operation is complete. If RESET# is asserted  
when a program or erase operation is not executing  
(RY/BY# pin is “1”), the reset operation is completed  
within a time of tREADY (not during Embedded Algo-  
rithms). The system can read data tRH after the RE-  
SET# pin returns to VIH.  
RESET#: Hardware Reset Pin  
The RESET# pin provides a hardware method of re-  
setting the device to reading array data. When the RE-  
SET# pin is driven low for at least a period of tRP, the  
device immediately terminates any operation in  
progress, tristates all output pins, and ignores all  
read/write commands for the duration of the RESET#  
pulse. The device also resets the internal state ma-  
chine to reading array data. The operation that was in-  
terrupted should be reinitiated once the device is  
ready to accept another command sequence, to en-  
sure data integrity.  
Refer to the AC Characteristics tables for RESET# pa-  
rameters and to Figure 15 for the timing diagram.  
Output Disable Mode  
When the OE# input is at VIH, output from the device is  
disabled. The output pins are placed in the high  
impedance state.  
Current is reduced for the duration of the RESET#  
pulse. When RESET# is held at VSS±0.3 V, the device  
Table 2. Am29DL640H Sector Architecture  
Sector Address  
Sector Size  
(Kbytes/Kwords)  
(x8)  
Address Range  
(x16)  
Address Range  
Bank  
Sector  
A21–A12  
SA0  
SA1  
0000000000  
0000000001  
0000000010  
0000000011  
0000000100  
0000000101  
0000000110  
0000000111  
0000001xxx  
0000010xxx  
0000011xxx  
0000100xxx  
0000101xxx  
0000110xxx  
0000111xxx  
0001000xxx  
0001001xxx  
0001010xxx  
0001011xxx  
0001100xxx  
0001101xxx  
0001110xxx  
0001111xxx  
8/4  
8/4  
000000h–001FFFh  
002000h–003FFFh  
004000h–005FFFh  
006000h–007FFFh  
008000h–009FFFh  
00A000h–00BFFFh  
00C000h–00DFFFh  
00E000h–00FFFFh  
010000h–01FFFFh  
020000h–02FFFFh  
030000h–03FFFFh  
040000h–04FFFFh  
050000h–05FFFFh  
060000h–06FFFFh  
070000h–07FFFFh  
080000h–08FFFFh  
090000h–09FFFFh  
0A0000h–0AFFFFh  
0B0000h–0BFFFFh  
0C0000h–0CFFFFh  
0D0000h–0DFFFFh  
0E0000h–0EFFFFh  
0F0000h–0FFFFFh  
00000h–00FFFh  
01000h–01FFFh  
02000h–02FFFh  
03000h–03FFFh  
04000h–04FFFh  
05000h–05FFFh  
06000h–06FFFh  
07000h–07FFFh  
08000h–0FFFFh  
10000h–17FFFh  
18000h–1FFFFh  
20000h–27FFFh  
28000h–2FFFFh  
30000h–37FFFh  
38000h–3FFFFh  
40000h–47FFFh  
48000h–4FFFFh  
50000h–57FFFh  
58000h–5FFFFh  
60000h–67FFFh  
68000h–6FFFFh  
70000h–77FFFh  
78000h–7FFFFh  
SA2  
8/4  
SA3  
8/4  
SA4  
8/4  
SA5  
8/4  
SA6  
8/4  
SA7  
8/4  
SA8  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
Bank 1  
10  
Am29DL640H  
June 7, 2005  
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