D A T A S H E E T
AC CHARACTERISTICS
1 cycle
wait state
when PS
enabled
4 cycles for initial access shown.
Programmable wait state function is set to 02h.
tCEZ
tCES
25 ns typ.
CE#
CLK
tAVDS
AVD#
tAVDH
tAVDO
tACS
tBDH
A16:
A21
Aa
tBACC
tACH
Hi-Z
A/DQ0:
A/DQ15
Aa
Da
tIACC
Da + 1
Da + 2
Da + n
tOEZ
OE#
RDY
tRACC
tOE
Hi-Z
Hi-Z
tRYDS
Notes:
1. Figure shows total number of clock cycles set to four.
2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency
is not present if PS is not enabled.
3. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and are indicated by RDY.
Figure 10. Burst Mode Read (40 MHz)
34
Am29BDS643G
25692A2 May 8, 2006
SPANSION [ SPANSION ]
