D A T A S H E E T
TEST CONDITIONS
Table 6. Test Specifications
3.3 V
65R,
70R
90R,
120R
Test Condition
Unit
2.7 kΩ
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
100
5
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
ns
V
0.0–3.0
Input timing measurement
reference levels
1.5
1.5
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
Figure 13. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 14. Input Waveforms and Measurement Levels
28
Am29BL802C
22371C7 November 3, 2006
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