P r e l i m i n a r y I n f o r m a t i o n
AC Characteristics
tCEZ
6
wait cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
CLK
tAVC
AVD#
tAVD
tACS
tBDH
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tACC
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY one cycle before valid data.
Figure 20. Linear Burst with RDY Set One Cycle Before Data
June 18, 2004 27024_A5_00_E
Am29BDS128H/Am29BDS064H
59
SPANSION [ SPANSION ]
