P r e l i m i n a r y I n f o r m a t i o n
AC Characteristics
Resume
x+1
Suspend
x
x+2
x+3
x+4
x+6
x+7
x+8
1
2
6
5
3
4
7
x+5
CLK
AVD#
t
t
OES
OES
A(n)
Addresses
t
CKA
OE#
Data(1)
RDY(1)
D(n)
D(n+2)
D(n+1)
3F
D(3F)
3F
D(40)
t
ACC
t
RACC
D(n+2) D(n+3) D(n+4) D(n+5)
Data(2)
RDY(2)
D(n+1)
D(n)
D(n+6)
t
RACC
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY with valid data.
1) RDY goes low during the two-cycle latency during a boundary crossing.
2) RDY stays high when a burst sequence crosses no boundaries.
Figure 25. Standard Handshake Burst Suspend prior to Initial Access
Resume
Suspend
x
1
6
9
x+2
5
x+1
2
3
4
7
8
x+3
CLK
AVD#
tOES
tOES
tOES
Addresses
OE#(1)
A(n)
tCKA
tCKA
tCKZ
D(n)
D(n)
D(n+1)
Data(1)
RDY(1)
tACC
tRACC
tRACC
tRACC
OE#(2)
Data(2)
D(n+2)
D(n+1)
D(n)
D(n+1)
tRACC
tRACC
tRACC
RDY(2)
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY with valid data.
1) Burst suspend during the initial synchronous access
2) Burst suspend after one clock cycle following the initial synchronous access
Figure 26. Standard Handshake Burst Suspend at or after Initial Access
62
Am29BDS128H/Am29BDS064H
27024_A5_00_E June 18, 2004
SPANSION [ SPANSION ]
