P r e l i m i n a r y I n f o r m a t i o n
AC Characteristics
Synchronous/Burst Read
Parameter
JEDEC Standard Description
75 MHz
66 MHz
54 MHz
Unit
Latency (Even address in Reduced
wait-state Handshaking mode)
tIACC
tIACC
tBACC
Max
Max
Max
49
56
69
ns
Latency (Standard Handshaking or
Odd address in Reduced wait-state
Handshaking mode
62
71
11
87.5
13.5
ns
ns
Burst Access Time Valid Clock to
Output Delay
9.3
tACS
tACH
tBDH
tCR
Address Setup Time to CLK (Note )
Address Hold Time from CLK (Note )
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Output Enable to Output Valid
Chip Enable to High Z
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
Min
Max
Max
Max
Min
Max
4
3
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
5.5
6
4
9.3
9.3
11
11
13.5
13.5
10
10
5
tOE
tCEZ
tOEZ
tCES
tRDYS
tRACC
tAAS
tAAH
tCAS
tAVC
tAVD
tACC
tCKA
tCKZ
tOES
tRCC
8
8
4
4
Output Enable to High Z
CE# Setup Time to CLK
RDY Setup Time to CLK
5
Ready Access Time from CLK
Address Setup Time to AVD# (Note )
Address Hold Time to AVD# (Note )
CE# Setup Time to AVD#
AVD# Low to CLK
9.3
5.5
11
13.5
5
4
6
0
7
4
5
12
55
13.5
10
5
AVD# Pulse
10
Access Time
45
50
11
CLK to access resume
9.3
CLK to High Z
8
4
Output Enable Setup Time
Read cycle for continuous suspend
1
Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
56
Am29BDS128H/Am29BDS064H
27024_A5_00_E June 18, 2004
SPANSION [ SPANSION ]
