A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram of Simultaneous
Sector Lock/Unlock Command Sequence ..............................23
Reset Command .....................................................................23
Autoselect Command Sequence ............................................24
Program Command Sequence ...............................................24
Unlock Bypass Command Sequence .....................................24
Figure 2. Erase Operation.............................................................. 25
Chip Erase Command Sequence ...........................................25
Sector Erase Command Sequence ........................................26
Erase Suspend/Erase Resume Commands ...........................26
Figure 3. Program Operation ......................................................... 27
Command Definitions .............................................................28
Table 13. Command Definitions .................................................... 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling .................................................................29
Figure 4. Data# Polling Algorithm .................................................. 29
RDY: Ready ............................................................................30
DQ6: Toggle Bit I ....................................................................30
Figure 5. Toggle Bit Algorithm........................................................ 30
DQ2: Toggle Bit II ...................................................................30
Table 14. DQ6 and DQ2 Indications .............................................. 31
Reading Toggle Bits DQ6/DQ2 ...............................................31
DQ5: Exceeded Timing Limits ................................................31
DQ3: Sector Erase Timer .......................................................32
Table 15. Write Operation Status ................................................... 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 6. Maximum Negative Overshoot Waveform ...................... 33
Figure 7. Maximum Positive Overshoot Waveform........................ 33
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Test Setup....................................................................... 35
Table 16. Test Specifications ......................................................... 35
Key to Switching Waveforms. . . . . . . . . . . . . . . . 35
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Input Waveforms and Measurement Levels ................... 35
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
VCC and VIO Power-up ..........................................................36
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7
Special Handling Instructions for FBGA Package ....................7
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .10
Table 1. Device Bus Operations ....................................................10
Enhanced VersatileIO™ (V ) Control ....................................10
IO
Requirements for Asynchronous Read
Operation (Non-Burst) ............................................................10
Requirements for Synchronous (Burst) Read Operation ........11
8-, 16-, and 32-Word Linear Burst with Wrap Around ............11
Table 2. Burst Address Groups .......................................................11
Burst Mode Configuration Register ........................................11
Handshaking Option ...............................................................12
Simultaneous Read/Write Operations with Zero Latency .......12
Writing Commands/Command Sequences ............................12
Accelerated Program Operation .............................................12
Autoselect Functions ..............................................................12
Standby Mode ........................................................................13
Automatic Sleep Mode ...........................................................13
RESET#: Hardware Reset Input .............................................13
Output Disable Mode ..............................................................13
Hardware Data Protection ......................................................13
Write Protect (WP#) ................................................................13
Low VCC Write Inhibit ..............................................................13
Write Pulse “Glitch” Protection ...............................................14
Logical Inhibit ..........................................................................14
Power-Up Write Inhibit ............................................................14
VCC and VIO Power-up And Power-down Sequencing .........14
Common Flash Memory Interface (CFI) . . . . . . .14
Table 3. CFI Query Identification String ..........................................14
Table 4. System Interface String .....................................................15
Table 5. Device Geometry Definition ..............................................15
Table 6. Primary Vendor-Specific Extended Query ........................16
Table 7. Sector Address Table ........................................................17
Command Definitions . . . . . . . . . . . . . . . . . . . . . .21
Reading Array Data ................................................................21
Set Burst Mode Configuration Register Command Sequence 21
Figure 1. Synchronous/Asynchronous State Diagram .................... 21
Read Mode Setting .................................................................21
Programmable Wait State Configuration ................................21
Table 8. Programmable Wait State Settings ...................................22
Handshaking Option ...............................................................22
Table 9. Initial Access Cycles vs. Frequency ..................................22
Non-Handshaking Operation ..................................................22
Table 10. Wait States for Non-Handshaking ...................................22
Burst Read Mode Configuration .............................................22
Table 11. Burst Read Mode Settings ..............................................23
Burst Active Clock Edge Configuration ...................................23
RDY Configuration ..................................................................23
Configuration Register ............................................................23
Table 12. Burst Mode Configuration Register .................................23
Figure 10. VCC and V Power-up Diagram................................... 36
IO
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Synchronous/Burst Read ........................................................37
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK).......................................................................... 38
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock) ..................................................................... 39
Figure 13. Synchronous Burst Mode Read.................................... 40
Figure 14. 8-word Linear Burst with Wrap Around......................... 40
Figure 15. Burst with RDY Set One Cycle Before Data ................. 41
Figure 16. Handshake Burst Mode Read
Starting at an Even Address .......................................................... 42
Figure 17. Handshake Burst Mode Read
Starting at an Odd Address............................................................ 43
Asynchronous Read ...............................................................44
Figure 18. Asynchronous Mode Read with Latched Addresses .... 44
Figure 19. Asynchronous Mode Read............................................ 45
Figure 20. Reset Timings............................................................... 46
Erase/Program Operations .....................................................47
Figure 21. Asynchronous Program Operation Timings.................. 48
Figure 22. Alternate Asynchronous Program Operation Timings... 49
Figure 23. Synchronous Program Operation Timings.................... 50
May 9, 2002
Am29BDS640G
3
SPANSION [ SPANSION ]
