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AM29BDS640GBD9WSI 参数 Datasheet PDF下载

AM29BDS640GBD9WSI图片预览
型号: AM29BDS640GBD9WSI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(4M ×16位) CMOS 1.8伏只同步读/写,突发模式闪存 [64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory]
分类和应用: 闪存内存集成电路
文件页数/大小: 65 页 / 845 K
品牌: SPANSION [ SPANSION ]
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A D V A N C E I N F O R M A T I O N  
Figure 22, Figure 24  
REVISION SUMMARY  
Added figures, which show different timings between  
addresses, CLK, WE#, and AVD#.  
Revision A (February 13, 2002)  
Initial release.  
Figure 25, Figure 27, Figure 28  
Revision A+1 (February 19, 2002)  
Automatic Sleep Mode  
Added note to indicate AVD# must toggle during data  
reads.  
Clarified description to indicate that sleep mode is acti-  
Figure 30, Figure 31  
vated when the first CLK edge occurs after tACC  
.
Shifted address, clock, and data cycle counts up by  
one.  
Figure 20, Asynchronous Program Operation  
Timings  
Revision A + 4 (July 26, 2002)  
Table 1, Device Bus Operations  
Modified to show that CLK is don’t care prior to AVD#  
going low, and that AVD# must not be low before CE#  
transitions low.  
Changed Synchronous Write to rising edge of CLK.  
Revision A+2 (February 27, 2002)  
Writing Commands/Command Sequences  
Figure 21, Asynchronous Program Operation  
Timings  
Added CLK as part of the asynchronous write opera-  
tion system drive.  
Extended don’t care section of CLK to falling edge of  
WE#.  
Added VCC and VIO Power-up and Power-down  
Sequencing section.  
Revision A+3 (May 9, 2002)  
AC Characteristics  
Requirements for Synchronous (Burst) Read  
Operation  
Changed tCHW erase/program time from Min to Max.  
Figure 20, Asynchronous Program Operation  
Timings  
Shifted address, clock, and data cycle references in  
third paragraph up by one.  
Changed tCSW1 reference to WE# from AVD#.  
Table 4, System Interface String  
Figure 21, Alternate Asynchronous Program  
Operation Timings  
Corrected data for address 23h.  
Table 9, Initial Access Cycles vs. Frequency  
Changed to show CLK low after tCHW time.  
Added table.  
Figure 22, Synchronous Program Operation  
Timings  
Autoselect Command Sequence  
Removed tACH.  
Added bottom boot device IDs to table.  
Changed tAHW to tAVSW and added tCSW2.  
Table 14, Command Definitions  
Added bottom boot device IDs to table.  
RDY: Ready  
Figure 23, Alternate Synchronous Program  
Operation Timings  
Changed tAVCH to tAVHC.  
Removed tACH.  
Corrected address boundary from 63rd word/3Eh to  
64th word/3Fh.  
DC Characteristics, CMOS Compatible  
DC Characteristics  
Corrected ICCB OE# = VIL to = VIH; switched Typ. and  
Max. values.  
Added VIO = VIO min to test conditions for VOL and VOH  
in table.  
Erase/Program Operations table  
Revision B (October 31, 2002)  
Added specifications for parameters tCSW1, tCSW2  
tCHW, tAHC  
,
Global  
.
Renamed Handshaking Enabled to Reduced  
Wait-State Handshaking  
Figure 21, Figure 23  
Added note to indicate AVD# must toggle during  
command sequence unlock cycles. Added tCSW1 to  
Figure 21.  
Renamed non-Handshaking to Standard Handshaking  
October 31, 2002  
Am29BDS640G  
63