A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following AVD# falling edge
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
Wait State Decoding Addresses:
A14, A13, A12 = “101”
A14, A13, A12 = “100”
A14, A13, A12 = “011”
A14, A13, A12 = “010”
A14, A13, A12 = “001”
A14, A13, A12 = “000”
5 programmed, 7 total
4 programmed, 6 total
3 programmed, 5 total
2 programmed, 4 total
1 programmed, 3 total
0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 32. Example of Wait States Insertion (Standard Handshaking Device)
October 31, 2002
Am29BDS640G
59
SPANSION [ SPANSION ]
