A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data
CLK
tACS
tAS
AVD#
tAH
555h
tAVDP
Addresses
Data
PA
VA
VA
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tAVSW
tWP
tWHWH1
tWPH
tWC
tCSW2
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
5. Either CS# or AVD# is required to go from low to high in
between programming command sequences.
2. “In progress” and “complete” refer to status of program
operation.
6. The Synchronous programming operation is independent
of the Set Device Read Mode bit in the Burst Mode
Configuration Register.
3. A21–A12 are don’t care during command sequence
unlock cycles.
7. CLK must not have an active edge while WE# is at VIL.
4. Addresses are latched on the first of either the rising edge
of AVD# or the active edge of CLK.
8. AVD# must toggle during command sequence unlock cy-
cles.
Figure 23. Synchronous Program Operation Timings
October 31, 2002
Am29BDS640G
51
SPANSION [ SPANSION ]
