A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAVHC
Read Status Data
CLK
tACS
tAS
AVD#
tAH
(Note 8)
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW2
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
6. The Synchronous programming operation is independent
of the Set Device Read Mode bit in the Burst Mode
Configuration Register.
2. “In progress” and “complete” refer to status of program
operation.
7. AVD# must toggle during command sequence unlock cy-
cles.
3. A21–A12 are don’t care during command sequence
unlock cycles.
8. tAH = 45 ns.
4. Addresses are latched on the first of either the rising edge
of AVD# or the active edge of CLK.
9. CLK must not have an active edge while WE# is at VIL.
5. Either CS# or AVD# is required to go from low to high in
between programming command sequences.
Figure 24. Alternate Synchronous Program Operation Timings
52
Am29BDS640G
October 31, 2002
SPANSION [ SPANSION ]
