A D V A N C E I N F O R M A T I O N
Figure 23. Synchronous Program Operation Timings..................... 51
Handshaking Device)..................................................................... 59
Figure 33. Back-to-Back Read/Write Cycle Timings...................... 60
Erase and Programming Performance . . . . . . . 61
FBGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . 61
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62
FBE080—80-ball Fine-Pitch Ball Grid Array (FBGA)
Figure 24. Alternate Synchronous Program Operation Timings ..... 52
Figure 25. Chip/Sector Erase Command Sequence....................... 53
Figure 26. Accelerated Unlock Bypass Programming Timing......... 54
Figure 27. Data# Polling Timings (During Embedded Algorithm) ... 55
Figure 28. Toggle Bit Timings (During Embedded Algorithm)......... 55
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings . 56
Figure 30. Latency with Boundary Crossing ................................... 57
Figure 31. Latency with Boundary Crossing
11 x 12 mm Package ..............................................................62
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63
into Program/Erase Bank................................................................ 58
Figure 32. Example of Wait States Insertion (Standard
4
Am29BDS640G
October 31, 2002
SPANSION [ SPANSION ]
