A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
7 cycles for initial access shown.
tCEZ
tCAS
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tAAS
tBDH
A21-A0
Aa
tBACC
tAAH
Hi-Z
DQ15
-
DQ0
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. A17 = 1.
Figure 13. Synchronous Burst Mode Read
7
cycles for initial access shown.
18.5 ns typ. (54 MHz)
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVDS
AVD#
tAVD
tACS
tBDH
Aa
A21-A0
tBACC
tACH
DQ15-DQ0
tIACC
tACC
D6
D7
D0
D1
D5
D6
OE#
RDY
tRACC
tOE
Hi-Z
tRDYS
Note: Figure assumes 7 wait states for initial access, 54 MHz clock, and automatic detect synchronous read. D0–D7 in data
waveform indicate the order of data within a given 8-word address range, from lowest to highest. Data will wrap around within
the 8 words non-stop unless the RESET# is asserted low, or AVD# latches in another address. Starting address in figure is the
7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register
command sequence has been written with A18=1; device will output RDY with valid data.
Figure 14. 8-word Linear Burst with Wrap Around
October 31, 2002
Am29BDS640G
41
SPANSION [ SPANSION ]
