A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Synchronous/Burst Read
Parameter
D8
D3
C8
C3
Description
(54 MHz) (54 MHz) (40 MHz) (40 MHz) Unit
JEDEC Standard
Latency (Even Address in Reduced
Wait-State Handshaking Mode)
tIACC
Max
87.5
95
ns
Parameter
D8, D9
D3, D4
C8, C9
C3, C4
Description
(54 MHz) (40 MHz) (40 MHz) (54 MHz) Unit
JEDEC Standard
Latency—(Standard Handshaking or
Odd Address in Handshake mode)
tIACC
Max
Max
106
120
20
ns
ns
Burst Access Time Valid Clock to Output
Delay
tBACC
13.5
tACS
tACH
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Output Enable to Output Valid
Chip Enable to High Z
Min
Min
Min
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
Min
Max
5
7
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBDH
tOE
13.5
20
tCEZ
10
10
10.5
10.5
10
10
10.5
10.5
tOEZ
Output Enable to High Z
tCES
CE# Setup Time to CLK
5
tRDYS
tRACC
tAAS
RDY Setup Time to CLK
5
4.5
14
5
4.5
20
Ready Access Time from CLK
Address Setup Time to AVD# (Note 1)
Address Hold Time to AVD# (Note 1)
CE# Setup Time to AVD#
AVD# Low to CLK
13.5
20
5
7
tAAH
tCAS
0
tAVC
5
tAVD
AVD# Pulse
12
70
tACC
Access Time
Note:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
38
Am29BDS640G
October 31, 2002
SPANSION [ SPANSION ]
