A D V A N C E I N F O R M A T I O N
INPUT/OUTPUT DESCRIPTIONS
A21-A0
=
Address inputs
AVD#
=
Address Valid input. Indicates to
device that the valid address is
present on the address inputs
(A21–A0).
DQ15-DQ0 = Data input/output
CE#
OE#
=
=
Chip Enable input. Asynchronous
relative to CLK for the Burst mode.
Low = for asynchronous mode,
indicates valid address; for burst
mode, causes starting address to be
latched.
Output Enable input. Asynchronous
relative to CLK for the Burst mode.
WE#
VCC
=
=
Write Enable input.
High = device ignores address inputs
Device Power Supply
(1.65 – 1.95 V).
RESET#
WP#
=
=
Hardware reset input. Low = device
resets and returns to reading array
data
VIO
=
Input & Output Buffer Power Supply
(either 1.65 – 1.95 V or 2.7 – 3.15 V).
Hardware write protect input. At VIL,
disables program and erase functions
in the two outermost sectors. Should
be at VIH for all other conditions.
VSS
=
=
=
=
Ground
VSSIO
NC
Output Buffer Ground
No Connect; not connected internally
ACC
=
At VID, accelerates programming;
automatically places device in unlock
bypass mode. At VIL, locks all sectors.
Should be at VIH for all other
conditions.
RDY
Ready output; indicates the status of
the Burst read. Low = data not valid at
expected time. High = data valid.
CLK
=
CLK is not required in asynchronous
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
LOGIC SYMBOL
22
A21–A0
16
DQ15–DQ0
CLK
WP#
ACC
CE#
OE#
WE#
RDY
RESET#
AVD#
October 31, 2002
Am29BDS640G
9
SPANSION [ SPANSION ]
