D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
Comments
32 Kword
4 Kword
128 Mb
64 Mb
0.4
0.2
103
54
5
5
Sector Erase Time
s
Excludes 00h programming prior to erasure
(Note 4)
s
s
Chip Erase Time
Word Programming Time
9
210
120
226.5
114
99
µs
µs
s
Accelerated Word Programming Time
4
Excludes system level overhead (Note 5)
Excludes system level overhead (Note 5)
128 Mb
75.5
38
Chip Programming Time
(Note 3)
64 Mb
s
128 Mb
33
s
Accelerated Chip
Programming Time
64 Mb
17
30
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally,
programming typicals assumes a checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 20, “Memory Array Command Definitions,” on page 46 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1 million cycles.
BGA BALL CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
4.2
5.4
3.9
Max
5.0
6.5
4.7
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
pF
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
84
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
SPANSION [ SPANSION ]
