D A T A S H E E T
AC CHARACTERISTICS
Address boundary occurs every 64 words, beginning at address
00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
C60
C61
3D
C62
3E
C63
3F
C63
3F
C63
3F
C64
40
CLK
3C
Address (hex)
(stays high)
AVD#
RDY(1)
RDY(2)
tRACC
tRACC
latency
tRACC
tRACC
latency
Data
Invalid
D60
D61
D62
D63
Read Status
OE#,
CE#
(stays low)
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a
bank in the process of performing an erase or program.
Figure 47. Latency with Boundary Crossing
into Program/Erase Bank
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
81
SPANSION [ SPANSION ]
