D A T A S H E E T
Table 21. Sector Protection Command Definitions
Bus Cycles (Notes 1–6)
First
Second
Third
Addr
Fourth
Fifth
Addr
Sixth
Data Addr Data
Seventh
Command Sequence
(Notes)
Addr Data Addr Data
Data
88
Addr
Data
Addr Data
Entry
Exit
3
4
555
555
AA
AA
2AA
2AA
55
55
555
555
90
XX
00
68
Protection Bit
Program (8, 9)
6
555
AA
2AA
55
555
60
SA+OW
SA+OW
48
OW
RD(0)
Program (11)
Verify (11)
4
4
7
6
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
38
C8
28
60
XX[0–3]
XX[0–3]
XX0
PD[0–3]
PD[0–3]
PD0
Unlock (11)
Program (8, 9)
XX1
PD1
48
XX2
XX
PD2
XX3
PD3
SBA+WP
68
SBA+WP
RD(0)
All Erase
SBA+
WPE
6
555
AA
2AA
55
555
60
WPE
60
40
XX
RD(0)
(8, 10, 12)
Status (13)
Set
4
3
4
4
4
4
555
555
555
555
555
555
AA
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
55
BA+555
555
90
78
58
48
48
58
SBA+WP
RD(0)
Status (8)
Write
BA+555
555
SA
SA
SA
SA
RD(1)
X1
Erase
555
X0
Status
BA+555
RD(0)
Locking Bit Program
(8, 9)
6
6
555
555
AA
AA
2AA
2AA
55
55
555
555
60
60
PL
SL
68
68
PL
SL
48
48
PL
SL
RD(0)
RD(0)
Locking Bit Program
(8, 9)
Legend:
X = Don’t care
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PA = Address of the memory location to be programmed. Addresses latch
on the rising edge of the AVD# pulse or active edge of CLK which ever
comes first.
PL = Address (A7–A0) is (00001010)
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1.
If unprotected, DQ0 = 0.
SA = Address of the sector to be verified (in autoselect mode) or erased.
Address bits Amax–A12 uniquely select any sector.
RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1.
If unprotected, DQ1 = 0.
BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for
which command is being written.
SBA = Sector address block to be protected.
SL = Address (A7–A0) is (00010010)
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
WD= Write Data. See “Configuration Register” definition for specific write
data
OW = Address (A7–A0) is (00011010).
PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations
that represent the 64-bit password.
WP = Address (A7–A0) is (00000010)
WPE = Address (A7–A0) is (01000010)
Notes:
1. See Table 1 for description of bus operations.
9. The fourth cycle programs the addressed locking bit. The fifth and
sixth cycles are used to validate whether the bit has been fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program
command must be issued and verified again.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, except
for RD, PD, WD, PWD, and PD3–PD0.
10. The fourth cycle erases all PPBs. The fifth and sixth cycles are used
to validate whether the bits have been fully erased. If DQ0 (in the
sixth cycle) reads 1, the erase command must be issued and verified
again.
5. Unless otherwise noted, address bits Amax–A12 are don’t cares.
6. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state. The
system must write the reset command to return the device to
reading array data.
11. The entire four bus-cycle sequence must be entered for each portion
of the password.
12. Before issuing the erase command, all PPBs should be programmed
in order to prevent over-erasure of PPBs.
7. No unlock or command cycles required when bank is reading array
data.
13. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not
set.
8. Not supported in Synchronous Read Mode, command mode verify
are always asynchronous read operations.
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
47
SPANSION [ SPANSION ]
