D A T A S H E E T
the starting location. The sixteen- and thirty-two linear
Standard Handshaking Option
wrap around modes operate in a fashion similar to the
eight-word mode.
For optimal burst mode performance on devices with
the standard handshaking option, the host system
must set the appropriate number of wait states in the
flash device depending on the clock frequency.
Table 17 shows the address bits and settings for the
four read modes.
Table 16 describes the typical number of clock cycles
(wait states) for various conditions with A14-A12 set to
101.
Table 17. Read Mode Settings
Address Bits
Burst Modes
A16
0
A15
0
Table 16. Wait States for Standard Handshaking
Continuous
Typical No. of Clock
Conditions at Address
Cycles after AVD# Low
8-word linear wrap around
16-word linear wrap around
32-word linear wrap around
0
1
Initial address
7
1
0
Initial address is 3E or 3Fh (or
offset from these addresses by
a multiple of 64) and is at
boundary crossing*
1
1
7
Note: Upon power-up or hardware reset the default setting is
continuous.
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising
edge of the clock after the initial synchronous access
time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set
so that the falling clock edge is active for all synchro-
nous accesses. Address bit A17 determines this set-
ting; “1” for rising active, “0” for falling active.
The autoselect function allows the host system to
determine whether the flash device is enabled for
handshaking. See the “Autoselect Command
Sequence” section on page 36 for more information.
Read Mode Configuration
RDY Configuration
The device supports four different read modes: contin-
uous mode, and 8, 16, and 32 word linear wrap around
modes. A continuous sequence begins at the starting
address and advances the address pointer until the
burst operation is complete. If the highest address in
the device is reached during the continuous burst read
mode, the address pointer wraps around to the lowest
address.
By default, the device is set so that the RDY pin will
output V whenever there is valid data on the outputs.
OH
The device can be set so that RDY goes active one
data cycle before active data. Address bit A18 deter-
mines this setting; “1” for RDY active with data, “0” for
RDY active one clock cycle before valid data. In asyn-
chronous mode, RDY is an open-drain output.
For example, an eight-word linear read with wrap
around begins on the starting address written to the
device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after
the previous eight word boundary, wrapping through
Configuration Register
Table 18 shows the address bits that determine the
configuration register settings for various device func-
tions.
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
35
SPANSION [ SPANSION ]
