D A T A S H E E T
Table 14. Programmable Wait State Settings
Total Initial Access
address bits A14–A12 to 010 for the system/device to
execute at maximum speed.
Table 15 describes the typical number of clock cycles
(wait states) for various conditions.
A14
A13
A12
Cycles
0
0
0
2
Table 15. Wait States for Reduced Wait-state
Handshaking
0
0
1
3
0
1
0
4
System
Frequency
Range
Device
Speed
Rating
0
1
1
5
Even Initial
Address
Odd Initial
Address
1
0
0
6
6–22 MHz
22–28 MHz
28–43 MHz
43–54 MHz
6–28 MHz
28–35 MHz
35–53 MHz
53–66 MHz
2
2
3
4
2
2
3
4
2
3
4
5
2
3
4
5
1
0
1
7 (default)
Reserved
Reserved
D
1
1
0
(54 MHz)
1
1
1
Notes:
1. Upon power-up or hardware reset, the default setting is
seven wait states.
E
2. RDY will default to being active with data when the Wait
State Setting is set to a total initial access cycle of 2.
(66 MHz)
It is recommended that the wait state command
sequence be written, even if the default wait state value
is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default set-
ting.
Notes:
1. If the latched address is 3Eh or 3Fh (or an address offset
from either address by a multiple of 64), add two access
cycles to the values listed.
2. In the 8-, 16-, and 32-word burst modes, the address
pointer does not cross 64-word boundaries (3Fh, or
addresses offset from 3Fh by a multiple of 64).
Reduced Wait-state Handshaking Option
If the device is equipped with the reduced wait-state
handshaking option, the host system should set
3. Typical initial access cycles may vary depending on
system margin requirements.
34
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
SPANSION [ SPANSION ]
