D A T A S H E E T
AC CHARACTERISTICS
tCEZ
tCES
7 cycles for initial access shown.
CE#f
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
tBDH
Addresses
Data
Aa
tBACC
tACH
Hi-Z
tIACC
tACC
Da
Da + 1
Da + n
tOEZ
OE#
RDY
tCR
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 16. CLK Synchronous Burst Mode Read (rising active CLK)
tCEZ
4 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
CLK
tAVC
AVD#
tAVD
tACS
tBDH
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tOE
tCR
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock)
58
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
SPANSION [ SPANSION ]
