D A T A S H E E T
AC CHARACTERISTICS
Synchronous/Burst Read
Parameter
Description
66 MHz
54 MHz
Unit
JEDEC
Standard
Latency (Even address in Reduced wait-state
Handshaking mode)
tIACC
Max
Max
Max
56
69
ns
Latency (Standard Handshaking or Odd
address in Reduced wait-state Handshaking
mode
tIACC
71
11
87.5
13.5
ns
ns
Burst Access Time Valid Clock to Output
Delay
tBACC
tACS
tACH
tBDH
tCR
Address Setup Time to CLK (Note )
Address Hold Time from CLK (Note )
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Output Enable to Output Valid
Chip Enable to High Z
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
Min
Max
Max
Max
Min
Max
4
6
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
3
4
11
11
8
13.5
13.5
10
10
5
tOE
tCEZ
tOEZ
tCES
tRDYS
tRACC
tAAS
tAAH
tCAS
tAVC
tAVD
tACC
tCKA
tCKZ
tOES
tRCC
Output Enable to High Z
CE# Setup Time to CLK
8
4
RDY Setup Time to CLK
Ready Access Time from CLK
Address Setup Time to AVD# (Note )
Address Hold Time to AVD# (Note )
CE# Setup Time to AVD#
AVD# Low to CLK
4
5
11
4
13.5
5
6
7
0
4
5
12
55
13.5
10
5
AVD# Pulse
10
50
11
8
Access Time
CLK to access resume
CLK to High Z
Output Enable Setup Time
Read cycle for continuous suspend
4
1
Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
57
SPANSION [ SPANSION ]
