Table 6. 16-Bit and 32-Bit Linear and Burst Data Order (Continued)
Data Transfer Sequence
(Independent of the WORD#
Output Data Sequence (Initial Access Address)
pin)
(x16)
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F (A2:A-1/ A3-A0 = 0000)
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 (A2:A-1/ A3-A0 = 0001)
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 (A2:A-1/ A3-A0 = 0010)
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 (A2:A-1/ A3-A0 = 0011)
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 (A:A-1/ A3-A0 = 0100)
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 (A2:A-1/ A3-A0 = 0101)
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 (A2:A-1/ A3-A0 = 0110)
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 (A2:A-1/ A3-A0 = 0111)
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 (A2:A-1/ A3-A0 = 1000)
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 (A2:A-1/ A3-A0 = 1001)
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 (A2:A-1/ A3-A0 = 1010)
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A (A2:A-1/ A3-A0 = 1011)
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B (A2:A-1/ A3-A0 = 1100)
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C (A2:A-1/ A3-A0 = 1101)
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D (A2:A-1/ A3-A0 = 1110)
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E (A2:A-1/ A3-A0 = 1111)
Sixteen Linear Data Transfers
(X16 Only)
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V (A3:A-1 = 00000)
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-0 (A3:A-1 = 00001)
:
Thirty-Two Linear Data Transfers
CE# Control in Linear Mode
U-V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T (A3:A-1 = 11110)
V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U (A3:A-1 = 11111)
RESET# Control in Linear Mode
The CE# (Chip Enable) pin enables the Am29BDD160
during read mode operations. CE# must meet the re-
quired burst read setup times for burst cycle initiation.
If CE# is taken to VIH at any time during the burst lin-
ear or burst cycle, the device immediately exits the
burst sequence and floats the DQ bus and IND/WAIT#
signal. Restarting a burst cycle is accomplished by
taking CE# and ADV# to VIL.
The RESET# pin immediately halts the linear burst ac-
cess when taken to VIL. The DQ data bus and
IND/WAIT# signal float. Additionally, the Configuration
Register contents are reset back to the default condi-
tion where the device is placed in asynchronous ac-
cess mode.
OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the lin-
ear burst data on the DQ data bus and the IND/WAIT#
pin. De-asserting the OE# pin to VIH during a burst op-
eration floats the data bus and the IND/WAIT# pin.
However, the device will continue to operate internally
as if the burst sequence continues until the linear burst
is complete. The OE# pin does not halt the burst se-
quence, this is accomplished by either taking CE# to
VIH or re-issuing a new ADV# pulse. The DQ bus and
IND/WAIT# signal remain in the float state until OE# is
taken to VIL.
ADV# Control In Linear Mode
The ADV# (Address Valid) pin is used to initiate a lin-
ear burst cycle at the clock edge when CE# and ADV#
are at VIL and the device is configured for either linear
burst mode operation. A burst access is initiated and
the address is latched on the first rising CLK edge
when ADV# is active or upon a rising ADV# edge,
whichever occurs first. If the ADV# signal is taken to
VIL prior to the end of a linear burst sequence, the pre-
vious address is discarded and subsequent burst
transfers are invalid until ADV# transitions to VIH be-
fore a clock edge, which initiates a new burst se-
quence.
IND/WAIT# Operation in Linear Mode
The IND/WAIT#, or End of Burst Indicator signal
(when in linear modes), informs the system that the
last address of a burst sequence is on the DQ data
bus. For example, if a 4-word linear burst access is
18
Am29BDD160G
June 7, 2006
SPANSION [ SPANSION ]
