If the device is deselected during erasure or program-
ming, the device draws active current until the opera-
tion is completed.
operation when RESET# was asserted, the user must
wait 11 µs before accessing that bank.
Asserting RESET# during a program or erase opera-
tion leaves erroneous data stored in the address loca-
tions being operated on at the time of device reset.
These locations need updating after the reset opera-
tion is complete. See Figure 19 for timing specifica-
tions.
ICC5 in the “DC Characteristics” section on page 53
represents the standby current specification.
Caution: entering the standby mode via the RESET#
pin also resets the device to the read mode and floats
the data I/O pins. Furthermore, entering ICC7 during a
program or erase operation will leave erroneous data
in the address locations being operated on at the time
of the RESET# pulse. These locations require updat-
ing after the device resumes standard operations.
Refer to the “RESET#: Hardware Reset Pin” section
for further discussion of the RESET# pin and its func-
tions.
Asserting RESET# active during VCC and VIO
power-up is required to guarantee proper device ini-
tialization until VCC and VIO have reached their steady
state voltages.
Output Disable Mode
See Table 1 Device Bus Operation for OE# Operation
in Output Disable Mode.
RESET#: Hardware Reset Pin
Autoselect Mode
The RESET# pin is an active low signal that is used to
reset the device under any circumstances. A logic “0”
on this pin forces the device out of any mode that is
currently executing back to the reset state. The RE-
SET# pin may be tied to the system reset circuitry. A
system reset would thus also reset the device. To
avoid a potential bus contention during a system reset,
the device is isolated from the DQ data bus by tristat-
ing the data output pins for the duration of the RESET
pulse. All pins are “don’t care” during the reset opera-
tion.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A1, and A0 must be as shown in Table 12 (top
boot devices) or Table 13 (bottom boot devices). In ad-
dition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits (see Tables 11 and 12). See Table 5
shows the remaining address bits that are don’t care.
When all necessary bits have been set as required,
the programming equipment may then read the corre-
sponding identifier code on DQ7–DQ0.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains low until the reset op-
eration is internally complete. This action requires
between 1 µs and 7µs for either Chip Erase or Sector
Erase. The RY/BY# pin can be used to determine
when the reset operation is complete. Otherwise,
allow for the maximum reset time of 11 µs. If RESET#
is asserted when a program or erase operation is not
executing (RY/BY# = “1”), the reset operation will com-
plete within 500 ns. Since the Am29BDD160 is a Si-
multaneous Operation device the user may read a
bank after 500 ns if the bank was in the read/reset
mode at the time RESET# was asserted. If one of the
banks was in the middle of either a program or erase
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
June 7, 2006
Am29BDD160G
15
SPANSION [ SPANSION ]
