F I N A L
AC CHARACTERISTICS
Parameter Symbols
Am27C040
JEDEC
Std.
Description
Test Setup
-90
-120 -150 -200
Unit
CE# = OE#
t
t
t
Address to Output Delay
Max
90
120
150
200
ns
AVQV
ACC
= V
IL
t
Chip Enable to Output Delay
OE# = V
Max
Max
90
40
120
50
150
65
200
75
ns
ns
ELQV
GLQV
CE
IL
t
t
t
Output Enable to Output Delay
Chip Enable High or Output Enable High,
CE# = V
OE
IL
t
EHQZ
GHQZ
DF
Max
Min
30
0
30
0
30
0
40
0
ns
ns
t
(Note 2) Whichever Occurs First, to Output High Z
Output Hold Time from Addresses, CE# or
OE#, Whichever Occurs First
t
t
OH
AXQX
Caution: Do not remove the device from (or inserted into) a socket when V or V is applied.
CC
PP
Notes:
1. V must be applied simultaneously or before V , and removed simultaneously or after V .
CC
PP
PP
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 1 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
2.0
0.8
2.0
0.8
Addresses Valid
Addresses
0.45
CE#/PGM#
OE#
t
CE
t
DF
t
OE
(Note 2)
t
ACC
t
OH
(Note 1)
High Z
High Z
Output
Valid Output
14971E-1
Note:
1. OE# may be delayed up to tACC - tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
CDV032
PD 032
PL 032
Typ
Parameter
Symbol
Parameter
Description
Test
Conditions
Typ
Max
12
Typ
Max
12
Max
10
Unit
pF
C
Input Capacitance
V
= 0 V
IN
10
12
10
12
8
9
IN
C
Output Capacitance V
= 0 V
15
15
12
pF
OUT
OUT
Notes:
1. This parameter is only sampled and not 100% tested.
2. T = +25°C, f = 1 MHz.
A
10
Am27C040