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AM26LV400BT-55RWAK 参数 Datasheet PDF下载

AM26LV400BT-55RWAK图片预览
型号: AM26LV400BT-55RWAK
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K的×8位/ 256千×16位) CMOS 3.0伏只引导扇区闪存 [4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory]
分类和应用: 闪存
文件页数/大小: 48 页 / 1129 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
DQ7, DQ6, or RY/BY#. See “Write Operation Status”  
for information on these status bits.  
Any commands written to the device during the Em-  
bedded Program Algorithm are ignored. Note that a  
hardware reset immediately terminates the program-  
ming operation. The Byte Program command se-  
quence should be reinitiated once the device has reset  
to reading array data, to ensure data integrity.  
START  
Write Program  
Command Sequence  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed  
from a “0” back to a “1”. Attempting to do so may  
halt the operation and set DQ5 to “1”, or cause the  
Data# Polling algorithm to indicate the operation was  
successful. However, a succeeding read will show that  
the data is still “0”. Only erase operations can convert  
a “0” to a “1”.  
Data Poll  
from System  
Embedded  
Program  
algorithm  
in progress  
Verify Data?  
Yes  
No  
Unlock Bypass Command Sequence  
The unlock bypass feature allows the system to pro-  
gram bytes or words to the device faster than using the  
standard program command sequence. The unlock  
bypass command sequence is initiated by first writing  
two unlock cycles. This is followed by a third write  
cycle containing the unlock bypass command, 20h.  
The device then enters the unlock bypass mode. A  
two-cycle unlock bypass program command sequence  
is all that is required to program in this mode. The first  
cycle in this sequence contains the unlock bypass pro-  
gram command, A0h; the second cycle contains the  
program address and data. Additional data is pro-  
grammed in the same manner. This mode dispenses  
with the initial two unlock cycles required in the stan-  
dard program command sequence, resulting in faster  
total programming time. Table 5 shows the require-  
ments for the command sequence.  
No  
Increment Address  
Last Address?  
Yes  
Programming  
Completed  
Note: See Table 5 for program command sequence.  
Figure 3. Program Operation  
During the unlock bypass mode, only the Unlock By-  
pass Program and Unlock Bypass Reset commands  
are valid. To exit the unlock bypass mode, the system  
must issue the two-cycle unlock bypass reset com-  
mand sequence. The first cycle must contain the pro-  
gram address and the data 90h. The second cycle  
need only contain the data 00h. The device then re-  
turns to reading array data.  
Chip Erase Command Sequence  
Chip erase is a six bus cycle operation. The chip erase  
command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional  
unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase  
algorithm. The device does not require the system to  
preprogram prior to erase. The Embedded Erase algo-  
rithm automatically preprograms and verifies the entire  
memory for an all zero data pattern prior to electrical  
erase. The system is not required to provide any con-  
trols or timings during these operations. Table 5 shows  
the address and data requirements for the chip erase  
command sequence.  
Figure 3 illustrates the algorithm for the program oper-  
ation. See the Erase/Program Operations table in “AC  
Characteristics” for parameters, and to Figure 17 for  
timing diagrams.  
Any commands written to the chip during the Embed-  
ded Erase algorithm are ignored. Note that a hard-  
ware reset during the chip erase operation  
immediately terminates the operation. The Chip Erase  
command sequence should be reinitiated once the de-  
16  
Am29LV400B  
21523D4 December 4, 2006