CXA3106Q
Pin
No.
Reference
voltage level
Symbol
I/O
Equivalent circuit
Description
Unlock signal output.
TTLVCC
This pin is an open collector output,
and pulls in the current when a phase
difference occurs. The UNLOCK
sensitivity can be adjusted by
17
UNLOCK
O
TTL
17
connecting a capacitor and resistors
to this output as appropriate.
(See the UNLOCK Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
TTLGND
IOGND
Inverted 1/2 clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
29
30
31
32
33
34
CLK/2L
CLK/2H
CLKL
O
O
O
O
O
O
PECL
PECL
PECL
PECL
PECL
PECL
1/2 clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
Inverted clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
IOVCC
PECLVCC
30 32 34
33
29 31
Clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
CLKH
IOGND
Delay sync signal output.
(See the I/O Timing Chart.)
This pin requires an external pull-
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
DSYNCL
DSYNCH
Inverted delay sync signal output.
(See the I/O Timing Chart.)
This pin requires an external pull-
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
– 9 –
SONY [ SONY CORPORATION ]
