CXA3106Q
Pin
No.
Reference
voltage level
Symbol
VCO
I/O
I
Equivalent circuit
Description
External VCO input.
Programmable counter test input
(controlled by a control register).
When using the VCO TTL input, open
the Pin 3 VCOH and Pin 4 VCOL
PECL inputs.
5
6
9
TTL
TTL
TTL
Phase detector disable signal.
Active high. When this pin is high, the
phase detector output is held. This pin
goes to high level when open.
HOLD
SYNC
I
I
(See the HOLD Timing Chart.)
Sync input.
When using the SYNC TTL input,
open the Pin 7 SYNCH and Pin 8
SYNCL PECL inputs.
The sync signal can be switched
between positive/negative polarity by
a control register.
IOVCC
r/2
Control signal (enable) for setting the
internal registers.
r
When SENABLE is low, registers can
be written; when high, registers can be
read.
(See the Control Register Table and
Control Timing Chart.)
5
6
9
10
11
12
13
10
SENABLE
I
TTL
1.5V
2r
Control signal (clock) for setting the
internal registers.
IOGND
When SENABLE is low, SDATA is
loaded to the registers at the rising
edge of SCLK.
When SENABLE is high, the register
contents are output from SEROUT at
the falling edge of SCLK.
11
SCLK
I
TTL
(See the Control Register Table and
Control Timing Chart.)
Control signal (data) for setting the
internal registers.
(See the Control Register Table and
Control Timing Chart.)
12
13
SDATA
TLOAD
I
I
TTL
TTL
Programmable counter test input.
This pin is normally open status and
high. Register contents can be loaded
immediately to Programmable counter
by setting TLOAD low during the
programmable counter test mode.
– 7 –
SONY [ SONY CORPORATION ]
