CXA3106Q
Pin
No.
Reference
voltage level
Symbol
I/O
Equivalent circuit
Description
IOVCC
Chip select.
When low, all circuits including the
register circuit are set to the power
save mode.
14
CS
I
TTL
14
When high, all circuits are set to
operating mode.
IOGND
Register read output.
When SENABLE is high, the register
contents are output from SEROUT at
the falling edge of SCLK.
(See the Control Register Timing
Chart.)
15
SEROUT
O
TTL
TTL output can be turned ON/OFF
(high impedance) by a control register.
Programmable counter test output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
16
20
21
22
23
DIVOUT
CLK/2N
CLK/2
CLKN
O
O
O
O
O
TTL
TTL
TTL
TTL
TTL
IOVCC
TTLVCC
100k
Inverted 1/2 clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
15 22
16 23
1/2 clock output.
20
21
24
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
TTLGND
IOGND
Inverted clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
Clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
CLK
Delay sync signal output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) and switched
between positive/negative polarity by
a control register.
24
DSYNC
O
TTL
– 8 –
SONY [ SONY CORPORATION ]
