CXA2089Q/S
Status register structure (DATA1 and DATA2)
" " indicates undefined.
b7
1
b6
0
b5
0
b4
1
b3
0
b2
0
b1
b0
1
Slave add.
ADR
DATA1
DATA2
S1SEL
S1SEL
S2SEL
S2SEL
S3SEL
S3SEL
S-C1
S-C3
S-C2
S1SEL to S3SEL (1 each): S-1 to S-3 pin status
0: S-1 to S-3 pins are not grounded.
1: S-1 to S-3 pins are grounded.
S1SEL to S3SEL are actually determined by comparing the S-1 to S-3 pin DC voltages with 3.5V.
S-1 to S-3 pin DC voltage
3.5V or more
S1SEL to S3SEL
0
1
3.5V or less
S-C1, S-C2, S-C3 (2 each): S2-1, S2-2 and S2-3 pin status
0: 4:3 video signal
1: 4:3 letter-box signal
2: 16:9 video squeezed signal
3: No signal
S-C1 to S-C3 are actually determined by comparing the S2-1 to S2-3 pin DC voltages with two
threshold. However, when the S-1 to S-3 pins are open, the outputs are fixed to "3".
S2-1 to S2-3 pin DC voltage
1.3V or less
S-C1 to S-C3
0
1
2
3
1.3V or more to 2.5V or less
2.5V or more
S-1 to S-3 OPEN
4) Power-on Reset
The CXA2089Q/S has an internal power-on reset function that sets each control register to "0" during IC power
ON.
The power-on reset VTH has hysteresis.
Power-on reset
released
Power-on reset
VCC
4.5V
5.6V
– 23 –
SONY [ SONY CORPORATION ]
